Entry Level Professional - Digital Design Engineer (Summer 2024 Start)

About the position

As an Entry Level Professional - Digital Design Engineer at Marvell, you will play a crucial role in the Custom Compute & Storage Business unit, where your primary responsibility will be to verify the circuitry that goes inside our chips designed for the general market and specific customers. These chips utilize cutting-edge technology to facilitate high-speed data transfers, and your work will ensure that each design meets the specifications set by our diverse clientele, which includes major telecom organizations and automotive companies. In this hybrid in-office/work-from-home role based in Westboro, MA, you will be involved in designing key components of System-On-Chips (SOCs) for Marvell's next generation of Accelerated Infrastructure processors. You will collaborate closely with architects, verification teams, physical design engineers, and other logic designers throughout the design process, which includes requirements specification, design execution, debugging, and achieving timing closure. Your ability to specify and present designs for review will be essential, as you will need to ensure that they meet feature, area, and performance requirements, as well as software programming needs. Your responsibilities will also include coding designs in Verilog, adhering to best RTL design practices to meet area estimates, targeted clock frequencies, and clock-domain-crossing requirements. You will support simulation-based and formal verification processes, explaining design behavior, defining stimulus and assertions, and debugging any issues that arise. Additionally, you will analyze static timing reports to optimize your logic and achieve timing closure. Participation in group-wide user and methodology groups will also be part of your role, allowing you to contribute to advancing general knowledge and best practices in chip design.

Responsibilities

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  Verify the circuitry inside chips for the general market and specific customers.
  
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  Design key components of System-On-Chips (SOCs) for next generation Accelerated Infrastructure processors.
  
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  Collaborate with architects, verification, physical design, and other logic designers for requirements specification, design execution, debug, and timing closure.
  
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  Specify and present designs for review that meet feature, area, and performance requirements.
  
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  Code designs in Verilog to meet area estimates, targeted clock frequencies, and clock-domain-crossing needs.
  
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  Support simulation-based and formal verification, explaining design behavior and debugging issues.
  
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  Analyze static timing reports to optimize logic for timing closure.
  
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  Participate in group-wide user and methodology groups to advance knowledge and best practices.
  

Requirements

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  Completed a Bachelor's Degree in Electrical Engineering or Computer Engineering with 2 to 3 years of related professional experience, or a Master's Degree/PhD in those fields.
  
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  Coursework must include analog classes, Verilog or VHDL, basic circuits, and computer architecture, with a focus in VLSI or related projects.
  
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  Experience using tools like Synopsys, Cadence, or Mentor for simulations.
  
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  Experience using Synopsys for synthesis and static timing analysis.
  
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  Comfortable working in a Linux environment and scripting with Python.
  
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  Detail-oriented with a readiness to iterate designs until refined.
  
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  Strong communication skills to keep the team informed about progress and issues.
  

Nice-to-haves

Benefits

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  Flexible time off
  
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  401k
  
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  Year-end shutdown
  
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  Floating holidays
  
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  Paid time off to volunteer
  

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